NOTE: For presentation at the conference site, 15 MINUTES in total are available for you.
Wednesday 8
| 8:00 | Registration |
| 9:00 | SPL2006 Inauguration and Plenary Conference |
| 10:30 | Coffee break |
| 11:00 | Session M1: DSP, Chairperson: Eduardo Boemo An FPGA-based System for the Measurement of Frequency Noise and Resolution of QCM Sensors Hardware Implementation of a an Optimal Pole Placement Controller for a Liquid Level System A Portable Hardware Design of a FFT Algorithm Sum-Subtract Fixed Point LDPC Decoder A soft-core for speech feature extraction |
| 12:30 | Lunch |
| 14:00 | Sesión M2: Vision I, Chairperson: Gustavo Sutter Real-time disparity map extraction in a dual head stereo vision system Forward and Inverse 2-D DCT Architectures for H.264/AVC Video Compression Directed to HDTV Pipeline Architecture for Real Time Morphological Color Image Processing |
| 15:00 | Session M3: Vision II, Chairperson: José Ignacio Martínez Torre Detecção de Movimento de Objetos em Tempo Real utilizando Dispositivos de Lógica Programável Complexa Diseño de una Arquitectura para La Segmentación de Imágenes Basados en Mean Shift en un FPGA Xilinx vs. Altera: Un Estudio Comparativo Síntesis de Circuitos Aritméticos Sobre FPGAs: Un Estudio Cuantitativo |
| 16:00 | Coffee break |
| 16:30 | Session M4: Embedded Processors I, Chairperson: Valentín Obac Roda Microcontrolador compatible con PIC16C84, bus Wishbone y video Diseño en Verilog de una Arquitectura Segmentada de Microprocesador RISC Puente IEEE1284 en modo EPP a bus Wishbone |
| 17:30 | Plenary Conference: Ph.D. Program on Digital Design at Univ. Autónoma of Madrid |
Thursday 9
| 9:00 | Plenary Conference |
| 10:00 | Session J1: Control & IP Cores I, Chairperson: Diego Gómez Vela High Speed Serial Data Ingestion Card A low cost approach using parallel techniques FPGA based stepper motor controller A Verilog HDL Digital Architecture for Delay Calculation Analysis and Implementation of Algorithms for
Localization and Mapping of Mobile Robots Based on
Reconfigurable Computing |
| 11:00 | Coffee break |
| 11:30 | Sesión J2: Arithmetic, Chairperson: Elías Todorovich AES-128 Cipher. Minimum Area, Low Cost FPGA Implementation Floating Point Multipliers with Reduced FPGA Area A fixed-point implementation of the Expanded Hyperbolic CORDIC Algorithm Comparison of FPGA Implementations of the mod m Reduction |
| 12:30 | Lunch |
| 14:00 | Session J3: Control & IP Cores II, Chairperson: José Alberto Díaz García Servicio Web de identificación biométrica sobre FPGA para dispositivos móviles Wi-Fi Interfaz Inteligente para Módulos de Potencia Trifásicos Medición de la posición angular con elevada resolución en accionamientos de alta dinámica Sistema Reconfigurável de Diagnóstico Remoto "Model Checkers" + "Proof Assistants" en la Verificación de Sistemas de Tiempo Real |
| 15:30 | Coffee break |
| 16:00 | Session J4: Education I, Chairperson: Elías Todorovich FPGALibre: Herramientas de Software Libre para diseño con FPGAs Diseño de un Filtro Digital (IIR) con Microprocesador de Arquitectura Multiciclo en FPGA Lógica Programable: La Experiencia Adquirida Durante Una Década de Diseño Enseñanza de VHDL para Informáticos |
Friday 10
| 9:00 | Session V1: EDA, Chairperson: Gustavo Sutter An Open-Source Tool for SystemC to Verilog Automatic Translation Functional verification: approaches and challenges Cells Life Cycle Applied to Digital Reconfiguration Design A VHDL Simulation Testbench Framework for Functional Verification of FPGA Designs Some Low Power Tips in FPGA Design |
| 10:30 | Coffee break |
| 11:00 | Sesión V2: Embedded Processors II, Chairperson: Ricardo Cayssials RtrASSoc51 - rI2C (reconfigurable Inter Integrated Circuit) uRT51: An Embedded Real-Time processor implemented on FPGA devices FPGA Design of an Efficient and Low-Cost Smart Phone Interrupt Controller |
| 12:00 | Session V3: Education II, Chairperson: Guillermo Güichal Kit de desarrollo educativo con CPLD Desarrollo de Plataformas Reconfigurables con Interfaz PCI como Proyecto de Grado Una Plataforma Didáctica Para el Aprendizaje de Técnicas de Diseño con Circuitos Lógicos Programables Entorno de Trabajo Integrado para la Reutilización de Código en el Diseño de Sistemas |
| 13:30 | Awards Ceremony and Concluding Remarks |