SPL 2010 Call for Papers

Authors are invited to submit original and unpublished contributions up to 6 pages to be considered as regular papers.

The page limit includes tables, figures and references. All contributions must be submitted electronically in PDF format.

The official language of the conference is English.

Guidelines and templates to prepare your papers are available in Downloads (IEEE format).

SPL 2010 organization has a pleasure to announce the IEEE Circuits and Systems Society (CAS) technical co-sponsorship. Accepted papers will appear in the IEEE Xplore electronic library, which provides excellent visibility and accessibility to its contents. On the other hand the conference editors will select the best papers whose authors will be invited to submit an extended version for publication in the International Journal of Reconfigurable Computing (ISSN: 1687-7195).

Please, feel free to publicize SPL 2010 by downloading and printing the conference POSTER .

Designer Forum

The goal of the Designer Forum is to give exposure to ongoing researches, academic experiences, and industrial designs in order to get feedback from experienced researchers and industrial partners. The accepted contributions to the Design Forum will not be included in the IEEE Database and SPL proceeding book. They will be published in a separate Designer Forum proceeding book, and these contributions will be presented in special poster sessions during the conference. Due to the regional scope of the Designer Forum, its papers can be written also in Spanish and Portuguese languages.

Authors interested in contributing to the Designer Forum are invited to submit 6-page papers.

Conference Topics

The Program Committee cordially invites you to participate and submit your contribution to SPL 2010. The conference topics are within the scope of field reconfigurable logic and its applications. A non exclusive list of themes is:

Design Methodology

  • Low-Power Design
  • High-speed Techniques
  • Physical Design
  • Synchronization and Seft-timed Systems
  • Dynamic and run-time reconfiguration
  • Reconfigurable embedded systems
  • Field-programmable analogue arrays
  • Interconnects and NoCs

FPGA in Education

  • Roadmap of programmable logic
  • Teaching reconfigurable systems
  • History and surveys of programmable logic
  • Emerging device technologies
  • Tutorials

Platform-based Design

  • Embedded Processors
  • Custom Computers
  • IP Cores
  • Java, Handel-C, System-C


  • Robotics
  • Artificial vision
  • Communications/networking/cryptography
  • Bioinformatics
  • Application acceleration
  • Evolvable and bio-inspired applications
  • Rapid prototyping

Signal Processing

  • Computer Arithmetics
  • Digital Signal Processing
  • Software Radio

EDA Tools

  • Logic and Architectural
  • Synthesis
  • Modelling and Simulation
  • Emulation
  • Formal Methods in System Design
  • CAD for reconfigurable architectures
  • System-level design methods
  • Testing, verification and benchmarking
  • Hardware/software co-design

High Reliability Embedded Applications

  • Design verification and validation
  • Reliability and fault tolerance
  • FIT rates analysis
  • Qualification process
  • Device obsolescence
  • High reliability processor cores
  • Noise, radiation effects and EMC
  • Experiences and lessons learned