Preliminary Program

Wednesday 1st of April, 2009

09:30 SPL 2009 Inauguration
10:15 Coffee break
Session W1: Reconfiguration and CAD

10:45 Experiences applying OVM 2.0 to an 8B/10B RTL design
Oswaldo Cadenas, Elías Todorovich
11:10 T-NDPack: Timing-Driven Non-Uniform Depopulation Based Clustering
Hanyu Liu, Ali Akoglu
11:35 PAM Map: An Architecture-Independent Logic Block Mapping Algorithm for SRAM-based FPGAs
Yun Shao, Jinmei Lai
12:00 Lunch

14:00 FPGA Accelerator for Protein Structure Prediction Algorithms
Advait Jain, Pulkit Gambhir, Priyanka Jindal, M Balakrishnan, Kolin Paul
14:25 Optimising multi-loop programs for heterogeneous computing systems
Yuet Ming Lam, Jose Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong
14:50 Comparing RTL and High-Level Synthesis Methodologies in the Design of a Theora Video Decoder IP Core
Leonardo Piga, Sandro Rigo
15:15 Design Space Exploration of PRESENT Implementations for FPGAs
Mohamad Sbeiti, Michael Silbermann, Axel Poschmann, Christof Paar
15:40 Coffee break

16:10 SCBXP: An efficient hardware-based XML parsing technique
Fadi El-Hassan, Dan Ionescu
16:35 CUBE: A 512-FPGA cluster
Oskar Mencer, Kuen Hung Tsoi, Stephen Craimer, Timothy Todman, Wayne Luk, Ming Yee Wong, Philip Heng Wai Leong
17:00 Flexible communication support for dynamically reconfigurable FPGAs
Ludovic Devaux, Daniel Chillet, Sebastien Pillement, Didier Demigny
17:25 Systolic array implementations for real time enhancement of remote sensing imaging
Alejandro Castillo Atoche, Jaime Ortegon Aguilar, Javier Vazquez Castillo
17:50 End of sessions

Thursday 2nd of April, 2009


8:30 Designing bio-inspired digital systems on custom FPGAs
Gianluca Tempesti - University of York - U. K.
10:00 Cofee break - Short paper session

10:40 What´s the future for programmable logic devices?
12:00 Lunch

Thursday 2nd of April, 2009


14:00 Parameterized Hardware Design on Reconfigurable Computers: An Image Registration Case Study
Miaoqing Huang, Olivier Serres, Tarek El-Ghazawi, Greg Newby
14:25 Power characterisation for the fabric in fine-grain reconfigurable architecture
Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa
14:50 A Population Coding Hardware Architecture for Spiking Neural Networks
Marco Aurelio Nuno-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil, Bernard Girau
15:15 FuSE - A Hardware Accelerated HDL Fault Injection Tool
Marcus Jeitler, Martin Delvai, Stefan Reichör
15:40 Coffee break

16:10 Reconfigurable Acceleration of 3D Image registration
Kuen Hung Tsoi, Daniel Rueckert, Chun Hok Ho, Wayne Luk
16:35 Decimal Addition in FPGA
Gery Bioul, Gustavo Sutter, Martín Vazquez, Jean-Pierre Deschamps
17:00 Concurrent calculations on reconfigurable logic devices applied to the analysis of video images
Sergio Geninatti, Manuel Hernández Calviño, José Ignacio Benavides Benítez, Nicolás Guil Mata
17:25 Fast Radix 2^k Dividers for FPGAs
Gustavo Sutter, Jean-Pierre Deschamps
17:50 End of sessions

Friday 3rd of April, 2009


08:30 Bio-inspired nano IC design: there is a lot of room in the middle!!!!
Fabrizio Lombardi - Northeastern University - U.S.A.
10:00 Cofee break - Designer Forum session

10:45 Real-time particle image velocimetry based on FPGA technology
José M. Iriarte Muñoz, Damián Dellavale, Maximiliano O. Sonnaillon, Fabián J. Bonetto
11:10 Hardware/software co-design using artificial neural network and evolutionary computing
Mauricio Acconcia Dias, Wilian Soares Lacerda
11:35 Rapid design space visualization through hardware/software partitioning
Simon A. Spacey, Wayne Luk, Paul H.J. Kelly, Daniel Kuhn
12:00 Lunch

14:00 Automatic VHDL generation for solving rotation and scale invariant template matching in FPGA
Henrique P. A. Nobre, Hae Yong Kim
14:25 A General Image Processing Architecture for FPGA
Fábio Cappabianco, Guido Araujo, Rodolfo Azevedo, Alexandre Falcão
14:50 FPGA/Soft-processor based real-time object tracking system
Usman Ali, Muhammad Bilal Malik, Khalid Munawar
15:15 Hardware accelerated aerial image simulation by FPGA
Hani Jamleh, Charlie Chung-Ping Chen
15:50 Conference closure ceremony


10:00 Thursday 2nd of April, 2009
Performance analysis of double digit decimal multiplier of various FPGA logic families
Rekha K. James, K. Poulose Jacob, Sreela Sasi
Mitigating and Tolerating SEU Effects in Switch Modules of SRAM-based FPGAs
Alireza Rohani, Hamid Reza Zarandi
SCAR-FPGA: A novel side-channel attack resistant FPGA
Ali Mokari, Behnam Ghavami, Hossein Pedram
Digital circuit evolution for scalability
Xiaoxuan She
Reconfigurable architecture for binay images invariant moments extraction
Guilherme H. R. Jorge , Valentin O. Roda, Juan Pablo Oliver, Julio Perez Acle, Sebastian Fernández
Dedicated system configurable via internet embedded communication manager module
María I. Schiavon, Daniel Crepaldo, Raúl Lisandro Martín, Carlos Varela
Test bench linux-based platform for power quality experiments
Ivan Llopard, Ricardo Cayssials, Edgardo Ferro, O. Alimenti
Flexible Configuration of Multi-Chip System using Actel FPGAs
Guillermo Guichal, Gaston Rodriguez, Mauro Koenig
Chopper-controlled PMDC motor driver using VHDL code
Marcelo F. Castoldi, Gabriel R.C. Dias, Manoel Luis de Aguiar, Valentin Obac Roda
Chipflow – a dynamic data flow machine using dynamic reconfigurable hardware
Jorge Luis e Silva, Joelmir J. Lopes, Valentin Obac Roda, Kelton Pontara da. Costa
Reducing reconfiguration times of FPGA-based systems using multi-level reconfiguration
Alexandre M. Amaral, Carlos A.P.S. Martins, Fernanda L.G. Kastensmidt
Design of asynchronous MSP 430 microprocessor using Balsa back-end retargeting
Sanghoon Kwak, Hyung-Woo Lee, Yousaf Zafar, Myeong-Hoon Oh, Dongsoo Har


10:00 Friday 3rd of April, 2009
FPGA/CPLD Design of wireless alarm system
Jing Pang, Drumil Jariwala, Nayankumar Patel
Descripcíon en VHDL de un sistema digital a partir de su modelizac~ion por medio de una red de Petri
Roberto Martínez, Javier Belmonte, Rosa Corti, Estela D’Agostino, Enrique Giandoménico
FPGA Implementation of Robust Asynchronous Controllers From Multi Burst Graph
Duarte Oliveira, Sandro S. Sato
Circuits with Floating-Gate Transistor
Alejandro Medina Santiago, Mario Alfredo Reyes
Proposal software design methodology for FPGA in space applications
Anderson Castellar, Evandro L. L. Rodrigues
A proposal of a quantum circuit simulator using FPGA
Renato O. Violin, José Hiroki Saito
Arquitetura em FPGA para o cálculo da Transformada de Distância Genérica em tempo real
Maximiliam Luppe
Conversion module for a dynamic data flow tool
Kelton Augusto Pontara da Costa, Valentin Obac Roda, Jorge Luiz e Silva