Workshops
Three days of intensive workshops will be organized to encourage hardware digital design skills on advance students and professionals. These workshops will be lectured by Xilinx, Satellogic and UAM experts in the field of hardware design and programmable logic. Everyone is welcome to attend these courses by simply registering.
| Topic | Affiliation | Duration | Time / Venue | Capacity |
| AWS F1 | Xilinx | full day | Sunday 7/ CADIEEL | 40 |
| PYNQ | Xilinx | full day | Monday 8 / CC Borges | 40 |
| SDSoC & HLS | UAM | Two days | Monday 8 and Tuesday 9/ CC Borges | 40 |
| COCOTB | Satellogic | full day | Tuesday 9 / CC Borges | 40 |
FPGA-based Accelerated Cloud Computing with AWS EC2 F1 and SDAccel
Tutorial Date and Time: April 7, 2019; 9:00 AM to 5:00 PM
Venue: CADIEEL, Cámara Argentina de Industrias Electrónicas, Electromecánicas y Luminotécnicas - Avda. Córdoba 950 4th Floor.
Presenter: Parimal Patel, XUP Senior Systems Engineer
Abstract: The increasing computational requirements of next-generation Cloud and High-Performance Computing (HPC) applications are pushing the adoption of accelerated computing based on heterogeneous architectures into mainstream, as traditional CPU technology is unable to keep pace. FPGA accelerators complement CPU-based architectures and deliver significant performance and power efficiency improvements.
In this regard, Xilinx FPGAs are now available on the Amazon Elastic Compute Cloud (EC2) F1 instances, which are designed to accelerate data center workloads, including machine learning inference, data analytics, video processing, and genomics. These are available in two different sizes that include up to eight Virtex® UltraScale+ VU9P FPGAs with a combined peak compute capability of over 170 TOP/sec (INT8). Furthermore, Amazon Web Services offers the SDAccel™ Development Environment for cloud acceleration, enabling the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto the heterogeneous CPU-FPGA system.
SDAccel completely automates the step of the hardware design flow, offering an easy to use environment for FPGA application design. It offers the possibility to specify a compute kernel using C and C++ for higher-level algorithmic implementation, or using hardware description languages for RTL designs, while using OpenCL APIs to control run-time behavior. The high performance and high-level of scalability offered by F1 instances, paired with the power and ease of use of Xilinx SDAccel, is very appealing for the development of high high-performance FPGA-based accelerated solutions, and will be the focus of this workshop.
Topics to be covered: Introduction to FPGA-based acceleration, development framework, platform, and use cases
Demonstration and hands-on-experience
- How to deploy an AWS EC2 F1 instance
- How to design using SDAccel with the Makefile flow
- How to design using SDAccel with the GUI flow
- Developing, profiling and optimizing F1 applications with SDAccel
- How to incorporate RTL IP in the SDAccel flow
- Debugging host application and kernels
- Introduction to Xilinx ML stack
Requirements: Attendees will use their laptops to connect to the WiFi network and use Amazon AWS
PYNQ: Python Productivity for Zynq
Tutorial Date and Time: April 8, 2019; 8:00 AM to 4:00 PM
Venue: CC Borges, Centro Cultural Borges - Corner of Viamonte and San Martín Galerias Pacífico Art and Shopping Mall.
Presenter: Parimal Patel, XUP Senior Systems Engineer
Abstract: PYNQ is an open-source framework that enables programmers who want to use embedded systems to exploit the capabilities of Xilinx Zynq SoCs. It allows users to exploit custom hardware in the programmable logic without having to use ASIC-style CAD tools. Instead the SoC is programmed in Python and the code is developed and tested directly on the embedded system. The programmable logic circuits are imported as hardware libraries and programmed through their APIs, in essentially the same way that software libraries are imported and programmed.
The framework combines four main elements: (1) the use of a high-level productivity language, Python in this case; (2) Python-callable hardware libraries based on FPGA overlays; (3) a web-based architecture incorporating the open-source Jupyter Notebook infrastructure served from Zynq's embedded processors; and (4) Jupyter Notebook's client-side, web apps. The result is a web-centric programming environment that enables software programmers to work at higher levels of design abstraction and to re-use both software and hardware libraries.
This tutorial will give a hands-on introduction to PYNQ framework using recently introduced PYNQ-Z2 board. It will feature the latest PYNQ release which includes an updated API, an optimized video pipeline, a simplified way of integrating new hardware and drivers into PYNQ, and developing, compiling, and deploying C-language code straight from the Jupyter notebook without opening Xilinx SDK tool.
Requirements: Attendees will use their laptops to connect to the PYNQ-Z2 boards
A Short-Bio Parimal Patel, XUP Senior Systems Engineer
Parimal received a Doctor of Philosophy in Electrical and Computer Engineering from the University of Texas at Austin, Texas in 1986.
In 1987 he joined the University of Texas as an Assistant Professor, got promoted to Associate and then to Full Professorships. During his tenure at the university he taught variety of courses including Logic Design, Digital Systems Design, Microcomputer Systems (peripheral interface principles), Embedded Systems Design, VLSI System Design, Computer Architecture, RISC Processor Design, Engineering Workstations, and Advanced HDL modeling.
Parimal has always enjoyed teaching and developing new courses. He started as a contract trainer and then full time employee of Xilinx developing variety of courses for Customer Education department. He joined the Xilinx University Program in April 2007 developing new courses, updating current courses, and delivering XUP workshops worldwide, including High-Level Synthesis, Embedded Systems, Advanced Embedded Systems, DSP Design Flow, DSP Implementation Techniques, Designing with SDSoC, Dynamic Partial Reconfiguration, Python Productivity on Zynq (PYNQ), and Accelerated Cloud Computing on AWS with SDAccel.
FPGA SoC design from a higher level of abstraction: SDSoC and HLS
Tutorial Date and Time: April 8 and 9, 2019; 9:00 AM to 5:00 PM
Venue: CC Borges, Centro Cultural Borges - Corner of Viamonte and San Martín Galerias Pacífico Art and Shopping Mall.
Presenter: Gustavo Sutter, UAM - Tobías Alonso, UAM
Course Contents: Introduction to FPGA. historical perspective, characteristics, strengths and weaknesses and future trends. Programing models and tools. Zynq Architecture and Introduction to Embedded System Design SDSoC “Software Defined System on a Chip” tool overview Handling data movements between the software and HW accelerators (Data motion networks) Coding Considerations Profiling: Profiling an application, analyzing the results, identifying function(s) for hardware implementation. Estimation: Estimating the expected performance of an application when functions are targeted in hardware, without going through the entire build cycle. Debugging: Debugging software application targeting Standalone and Linux OS in SDSoC. Using C-callable libraries and multiple accelerators Introduction to Vivado-HLS (High Level Syntesis). Techniques, Directives and IP generation. Improving performance in SDSoC with Vivado HLS.
Requirements:
- Basic on digital design (VHDL or Verilog will be a plus)
- Basic on microcontrollers and C/C++ languages
- Laptop with SDSoc 2018.3 installed
A Short-Bio
Gustavo Sutter
Doctor por la Universidad Autónoma de Madrid, Ingeniero en Sistemas en la Univ. Nacional del Centro de la Prov. de Buenos Aires. Cuenta con más de 15 años de experiencia en diseño de sistemas basados en FPGA. Se especializa en el área de arquitectura de ordenadores, diseños digitales, aritmética de computadores y computación de altas prestaciones. Ha colaborado en múltiples proyectos de investigación nacionales, europeos y de transferencia con empresas. Ha escrito tres libros y más de un centenar de comunicaciones técnicas. Ha dictado cursos en diferentes Universidades y participa activamente en la formación para empresas. Actualmente es docente e investigador en la Escuela Politécnica Superior de la Universidad Autónoma de Madrid y coordina tareas en ElectraTraining para la formación y transferencia en temas de sistemas embebidos, diseño de PCBs y FPGAs.
Tobías Alonso
Ingeniero Electrónico por la Universidad Nacional de San Juan en Argentina. Desarrolla su doctorado sobre diseño de circuitos desde alto nivel en la Escuela Politécnica Superior de la Universidad Autónoma de Madrid. Ha participado en múltiples proyectos de Investigación e I+D sobre diseño FPGA.
Testbenchs in Python: COCOTB
Tutorial Date and Time: April 9, 2019; 9:00 AM to 5:00 PM
Venue: CC Borges, Centro Cultural Borges - Corner of Viamonte and San Martín Galerias Pacífico Art and Shopping Mall.
Presenter:Andres Julio Demski
Abstract: COCOTB is a framework opensource which allows you to use Python for developing testbenchs. Basically, It is a Python frontend for interacting with a simulator and it supports multiples operative systems and HDL simulators. Firstly, We are going to start doing a python introduction, followed by an explanation of other tools like docker, gtkwave, iverilog, among others opensource tools. After that, we are going to present COCOTB, explaining the architecture and functionalities. We will show several examples and do some workshops. Finally, we will compare this tool with others frameworks like UVM, UVVM or OVM and we will draw conclusions.
Requirements:
- Basic Linux knowledge
- HDL knowledge
- Notebook
A Short-Bio Andres Julio Demski:
Andres is an Electronic Engineer graduated from the UTN, Buenos Aires, Argentina. He have been working in Satellogic for two years, designing high speed devices for satellites. He have wide experience validating cores and generating environments for testing and continuous integration. Andres is an opensource lover and uses them whenever possible.
Technical Sponsorship
Institutional Sponsors
